The invention relates generally to integrated circuits, and more particularly to a method and apparatus for generating pipeline hazard test sequences.
In order to maximize the utilization and throughput of a limited set of resources included in a circuit, pipelining techniques are used to move data through the circuit in an organized fashion such that different portions of the circuit are acting upon different portions of the data at the same time. Such pipelining techniques are well known in the art, and as the complexity of integrated circuits increases, the depth, or number of stages included in such pipelines is also increasing. Deep pipeline structures (those that include many stages) are included in integrated circuits such as digital signal processors (DSPs), microprocessors, microcontrollers, etc. These types of integrated circuits utilize an instruction set to determine the specific operations performed both within the pipeline and in the peripheral circuitry surrounding the pipeline.
Different instructions executed on such circuits utilize different resources within the pipeline structure. The resources utilized can include memory structures, registers, and functional units such as adders, multipliers, complex arithmetic logic units, and the like. When multiple instructions are concurrently executing within the pipeline that require the use of the same resource at the same time, hazard conditions arise. Such hazard conditions can cause errors if not eliminated, and a great deal of time and effort is typically spent during the design and debug of such integrated circuits in an attempt to eliminate all of the potential hazards that may exist.
Because of the depth of typical pipelines included in complex integrated circuits today, most techniques for detecting and eliminating hazards are limited such that some hazards may not be eliminated, or those hazards detected may be eliminated in a manner that overcompensates for the potential resource utilization conflict. As such, integrated circuits may be manufactured and marketed that either include functional bugs or suffer from lower performance due to attempts to eliminate hazards that overcompensate in their attempts to correct the potential timing issues.
Although some prior art attempts to detect hazard conditions in deep pipeline structures have been developed, these prior art attempts do not provide the flexibility, accuracy, or completeness of coverage desired. For example, detection of hazards corresponding to the use of condition codes that are often present in microcontroller and microprocessor designs are not supported in some of these prior art attempts. Other prior art attempts to detect hazards rely on automatic test program generation to create sequences of instructions that are executed to detect hazards. However, because a large number of instructions are typically supported by a microprocessor, the number of potential combinations of instructions makes complete coverage difficult to achieve using such prior art automatic test generation techniques.